1. Field of the Invention
The present disclosure relates to semiconductor structures and, more specifically, to embodiments of a semiconductor structure that incorporates a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure.
2. Description of the Related Art
As technology scaling continues, the size of middle of the line (MOL) contacts for semiconductor devices in advanced very large-scale integrated (VLSI) circuits is shrinking, leading to increased parasitic resistance. The minimum dielectric spacing between a contact and other conductive semiconductor device components (e.g., the minimum dielectric spacing between a source/drain region contact and a gate structure in the case of a field effect transistor (FET)) is also shrinking, leading to an increase parasitic capacitance as well as a corresponding increase in the probability of a short. The increases in parasitic resistance, parasitic capacitance and the probability of a short, in turn, impact semiconductor device performance and reliability. Additionally, rapid adoptions of new device component materials (e.g., in the case of FETs, rapid adoptions of metal gate conductors, epitaxial silicon germanium (SiGe) source/drain regions, copper contacts, etc.) and rapid adoptions of new device configurations (e.g., in the case of FETs, rapid adoptions of raised source/drain regions, stress layers, fin-type semiconductor bodies, etc.) have further exacerbated these issues. Unfortunately, since an increase in contact size decreases parasitic resistance, but also increases parasitic capacitance and the probability of a short for a semiconductor device of a given size because of the corresponding decrease in dielectric spacing, and since an increase in dielectric spacing decreases parasitic capacitance and the probability of a short, but also increases parasitic resistance for a semiconductor device of a given size because of the corresponding decrease in contact size, semiconductor device design typically involves a trade-off between contact size and dielectric spacing.